Question : Problem: 440 LX Chipset.

I've seen a list of Pentium II m/b. Most of them carry the name 440 LX. what does that mean? Is it the Intel chipset model?

I also heard that there is a newer version of this chipset comming out. Can you pls tell me about it? I think it's BX.

Thanks.

Answer : Problem: 440 LX Chipset.

the 440LX is the latest AGP PII Chipset from Intel.

LONG DESC:
Intel 440LX AGPset

Specifications

     Supports the Pentium II Processor with a bus speed of 66MHz officially, or 83MHz to 100MHz unofficially
          Supports 32-Bit Addressing
          Optimized In-Order and Request Queue
          Full Symmetric Multi-Processor (SMP) protocol for Up to Two Processors
          Dynamic Deferred Transaction Support
          GTL+ Compliant Host Bus Supports WC Cycles

     Integrated DRAM Controller
          EDO and SDRAM Support
          Supports a Maximum of 512MB SDRAM, or 1GB EDO
          64/72-bit Path to Memory
          Configurable DRAM Interface
          8 RAS Lines Available
          Support for 4-, 16- and 64-Mbit DRAM Devices
          Support for Symmetrical and Asymmetrical DRAM Addressing
          Configurable Support for ECC/EC
          ECC With Single Bit Error Correction and Multiple Bit Error Detection
          Read-Around-Write Support for Host and PCI DRAM Read Accesses
          Supports 3.3V DRAMs

     Accelerated Graphics Port (AGP) Interface
          AGP Specification Compliant
          AGP 66/133MHz 3.3V Devices Supported
          Synchronous Coupling to the Host Bus Frequency

     PCI Bus Interface
          PCI Revision 2.1 Interface Compliant
          Greater Than 100-MBps Data Streaming for PCI-to-DRAM Accesses
          Integrated Arbiter with Multi-Transaction PCI Arbitration Acceleration Hooks
          Five PCI Bus Masters are Supported in Addition to the Host and PCI-to-ISA I/O Bridge
          Delayed Transaction Support

     Data Buffering for Increased Performance
          Extensive CPU-to-DRAM, PCI-to-DRAM, and AGP-to-DRAM Write Data Buffering
          CPU-to-AGP, PCI-to-AGP, and AGP-to-PCI Burst Writes
          Supports Concurrent Host, PCI, and AGP Transactions to Main Memory

     System Management Mode (SMM) Compliant
     492 Pin BGA Package

The 82443LX (PAC) is the first generation of desktop AGPset designed for the Pentium II processor. The 82443LX PCI AGP
Controller (PAC) integrates a Host-to-PCI bridge, optimized DRAM controller and data path, and an Accelerated Graphics Port
(AGP) interface. AGP is a high performance, component level interconnect, targeted at 3D graphics applications and based on a
set of performance enhancements to PCI. The I/O subsystem portion of the PAC platform is based on the PIIX4, a highly
integrated version of the Intel’s PCI-to-ISA bridge family. PAC is developed as the ultimate Pentium II processor platform and is
targeted for emerging 3D graphics and multimedia applications. The 440LX AGPset may contain design defects or errors known
as errata which may cause the product to deviate from published specifications. Current characterized errata are available on
request.
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This is all I could find about the 440BX Chipset (according to INTEL)

Intel® 440BX AGPset

Does the Intel® 440BX AGPset support the Pentium® Pro processor?
No, the Intel 440BX AGPset supports the Pentium® II processor.
What is the cacheability of the Intel 440BX AGPset?
As the L2 cache and tag RAM are internal to the Pentium
II processor, the system cahceability is dependent on
the cacheability of the processor.

Is the 100 MHz SDRAM spec available?
The PC SDRAM, PC Unbuffered DIMM, and PC Serial
Presence Detect Memory Specifications are available on
the developer.intel.com web site.

How much system memory can the Intel 440BX AGPset support?
The Intel 440BX AGPset supports up to 4 double sided
DIMMs (8 rows memory), which allows up to 512MB of
system memory when using Unbuffered DIMMs or 1GB
when using Registered DIMMs.

Does the Intel 440BX AGPset support mixed memory types on a row by row basis?
The Intel 440BX AGPset does not support mixing
Unbuffered DIMMs and Registered DIMMs on a row by row basis.

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