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Question : Problem: need help translating VHDL to verilog
Hi,
I only know verilog and i'm still learning. can someone help me to translate this to verilog? thx alot
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-- vga_main.vhd Demo VGA configuration module.
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-- Author: Barron Barnett
-- Copyright 2004 Digilent, Inc.
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--
-- This project is compatible with Xilinx ISE or Xilinx WebPack tools.
--
-- Inputs:
-- mclk - System Clock
-- Outputs:
-- hs - Horizontal Sync
-- vs - Vertical Sync
-- red - Red Output
-- grn - Green Output
-- blu - Blue Output
--
-- This module creates a three line pattern on a vga display using a
-- a vertical refresh rate of 60Hz. This is done by dividing the
-- system clock in half and using that for the pixel clock. This in
-- turn drives the vertical sync when the horizontal sync has reached
-- its reset point. All data displayed is done by basic value
-- comparisons.
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-- Revision History:
-- 07/01/2004(BarronB): created
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.AL
L;
entity vgaController is
Port ( mclk : in std_logic;
hs : out std_logic;
vs : out std_logic;
red : out std_logic;
grn : out std_logic;
blu : out std_logic);
end vgaController;
architecture Behavioral of vgaController is
constant hpixels : std_logic_vector(9 downto 0) := "1100100000"; --Value of pixels in a horizontal line
constant vlines : std_logic_vector(9 downto 0) := "1000001001"; --Number of horizontal lines in the display
constant hbp : std_logic_vector(9 downto 0) := "0010010000"; --Horizontal back porch
constant hfp : std_logic_vector(9 downto 0) := "1100010000"; --Horizontal front porch
constant vbp : std_logic_vector(9 downto 0) := "0000011111"; --Vertical back porch
constant vfp : std_logic_vector(9 downto 0) := "0111111111"; --Vertical front porch
signal hc, vc : std_logic_vector(9 downto 0); --These are the Horizontal and Vertical counters
signal clkdiv : std_logic; --Clock divider
signal vidon : std_logic; --Tells whether or not its ok to display data
signal vsenable : std_logic; --Enable for the Vertical counter
begin
--This cuts the 50Mhz clock in half
process(mclk)
begin
if(mclk = '1' and mclk'EVENT) then
clkdiv <= not clkdiv;
end if;
end process;
--Runs the horizontal counter
process(clkdiv)
begin
if(clkdiv = '1' and clkdiv'EVENT) then
if hc = hpixels then --If the counter has reached the end of pixel count
hc <= "0000000000"; --reset the counter
vsenable <= '1'; --Enable the vertical counter to increment
else
hc <= hc + 1; --Increment the horizontal counter
vsenable <= '0'; --Leave the vsenable off
end if;
end if;
end process;
hs <= '1' when hc(9 downto 7) = "000" else '0'; --Horizontal Sync Pulse
process(clkdiv)
begin
if(clkdiv = '1' and clkdiv'EVENT and vsenable = '1') then --Increment when enabled
if vc = vlines then --Reset when the number of lines is reached
vc <= "0000000000";
else vc <= vc + 1; --Increment the vertical counter
end if;
end if;
end process;
vs <= '1' when vc(9 downto 1) = "000000000" else '0'; --Vertical Sync Pulse
red <= '1' when (hc = "1010101100" and vidon ='1') else '0'; --Red pixel on at a specific horizontal count
grn <= '1' when (hc = "0100000100" and vidon ='1') else '0'; --Green pixel on at a specific horizontal count
blu <= '1' when (vc = "0100100001" and vidon ='1') else '0'; --Blue pixel on at a specific vertical count
vidon <= '1' when (((hc < hfp) and (hc > hbp)) or ((vc < vfp) and (vc > vbp))) else '0'; --Enable video out when within the porches
end Behavioral;
Answer : Problem: need help translating VHDL to verilog
A the momento I have not a compiler, so my translation could contain typos or some syntax error:
_______________
module vgaController(mclk,hs,vs,r
ed,grn,blu
);
`define hpixels 10'b1100100000 // Value of pixels in a horizontal line
`define vlines 10'b1000001001 // Number of horizontal lines in the display
`define hbp 10'b0010010000 // Horizontal back porch
`define hfp 10'b1100010000 // Horizontal front porch
`define vbp 10'b0000011111 // Vertical back porch
`define vfp 10'b0111111111 // Vertical front porch
input mclk;
output hs,vs,red,grn,blu;
reg [9:0] hc,vc; // These are the Horizontal and Vertical counters
reg clkdiv; // Clock divider
wire vidon; // Tells whether or not its ok to display data
reg vsenable; // Enable for the Vertical counter
// continous assignments
assign hs = (hc[9:7]==3'b000) ? 1 : 0; // Horizontal Sync Pulse
assign vs = (vc[9:1]==9'b000000000) ? 1 : 0; // Vertical Sync Pulse
assign red = (vidon & (hc[9:0]==10'b1010101100))
? 1 : 0; // Red pixel on at a specific horizontal count
assign grn = (vidon & (hc[9:0]==10'b0100000100))
? 1 : 0; // Green pixel on at a specific horizontal count
assign blu = (vidon & (hc[9:0]==10'b0100100001))
? 1 : 0; // Blue pixel on at a specific horizontal count
assign vidon = (((hc[9:0] < `hfp) & (hc[9:0] > `hbp)) | ((vc[9:0] < `vfp) & (vc[9:0] > vbp))) ? 1 : 0; // Enable video out when within the porches
// This cuts the 50Mhz clock in half
always @(posedge mclk)
begin
clkdiv <= !clkdiv;
end
// Runs the horizontal counter
always @(posedge clkdiv)
begin
if (hc[9:0]==`hpixels) // If the counter has reached the end of pixel count
begin
hc[9:0] <= 0; // reset the counter
vsenable <= 1; // Enable the vertical counter to increment
end
else
begin
hc[9:0] <= hc[9:0] + 1; // Increment the horizontal counter
vsenable <= 0; // Leave the vsenable off
end
end
//
always @(posedge clkdiv)
begin
if (vsenable) // Increment when enabled
begin
if (vc[9:0]==`vlines ) // If the counter has reached the end
begin
vc[9:0] <= 0; // Reset when the number of lines is reached
end
else
begin
vc[9:0] <= vc[9:0] + 1; // Increment the vertical counter
end
end
end
end module
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