Everything is in the "Complete Documentation" pdf.
Figure 111 on page 573 shows all the control registers you use to manage the ATD.
The register map on pages 559-560 show the individual control/status bits.
ATDCTL0 and 1 are reserved, so ignore them.
ATDCTL2 and 3 control the configuration of the ATD module. You choose a value for all the control bits, put them together into bytes, then write these bytes to each control register.
ATDCTL2:
ADPU : set to 1, you want it powered on and working. This needs to be set for a little while before the ATD module can be used. How long? I don't know.
AFFC: do you want to use a polling loop to check for the conversion complete flag, or do you want to be interrupted? I suspect a polling loop will do because you don't have anything better to do. So set this to 0 to use normal mode
AWAI: I don't think you need to worry about power consumption, so set this to 0
ETRIGLE, ETRIGP, ETRIGE, see table 96 on page 566. You are using an internal timer, not an external trigger, so you only need to make sure you set ETRIGE to 0. Might as well set the other two to 0 too.
ASCIE: I assume you will be polling the conversion complete flag, so disable the interrupt. set to 0.
ASCIF: This is read-only, so don't worry about it.
ATDCTL3
bit 7 is ignored.
S8C,S4C,S2C,S1C: You are only doing one conversion at a time, so set them to 0,0,0,1 respectively.
FIFO: Enabling this causes each new conversion to be written into the next result register, cycling around the result registers. You don't want this, it should just write each result into the same register every time. So set it to 0.
FRZ0,FRZ1: depends on how you want the debugging behavior to be. If you're not debugging, anything will do here.
ATDCTL4 and 5 are special registers, in that they enable you to configure the ATD module, and they trigger a whole ATD conversion sequence when you write to either one of them. If you write to one of them while it is in the middle of a conversion sequence, the sequence is aborted and a new sequence begun.
ATDCTL4:
SRES8: I'm guessing you want 10-bit resolution, not 8. So set it to 0.
SMP1,SMP0: This controls how long the ATD takes to carefully store a copy of the original signal's value into the sample storage capacitor. Longer is a little better. Time isn't a critical factor, so might as well use the highest setting. Set to 1 and 1.
PRS4-0: I don't understand the ramifications of this setting. Maybe performance vs. power consumption? So just pick a value somewhere in the middle. 0/1/0/0/0 or so.
ATDCTL5:
DJM: You probably want the result right-justified since you're just displaying it and not doing any fancy math with it. So set it to 1.
DSGN: We're using right-justified mode, so set it to 0.
SCAN: just want to do one conversion each time, so set to 0.
MULT: Only want one channel, so set to 0.
bit 3 is ignored
CC/CB/CA: channel 0 right? So set to 0/0/0
You only need to check one bit in the ATDSTAT register, and it can be either SCF or CCF0.
So the whole process goes like this:
initialization:
Write configuration values to ATDCTL2, ATDCTL3, and ATDCTL4. Writing to ATDCTL4 triggers a conversion sequence whose result we can ignore.
When a timer interrupt occurs:
Write the control value to ATDCTL5.
Poll the ATDSTAT register until a completion bit is set.
Read the result value out of ATDDR0H and ATDDR0L.
Send the result value to the 7-segment display
