Question : Problem: Tcl/Tk scripting for VHDL models

Hello,
     I need one or two examples in tcl/tk scripting for testing vhdl model.The model can be a halfadder,multiplexer or any small sequential circuits.Can anyone help me.

Answer : Problem: Tcl/Tk scripting for VHDL models

Ok, first of all you have to execute a simulation. In the wave window, after you configured everything, save the format of the window and signals in "wave.do" file (it is the fastest way to write the wave.do file).

Create a macro file "mymacro.do" containing:

quit -sim
vcom file1.vhd
vcom file2.vhd
vcom file3.vhd
vcom top.vhd
vcom testbench.vhd
vsim work.testbench
view wave
do wave.do
run -all


Then in Modelsim console execute the macro with the following command:

do mymacro.do


Maybe you would need to customize further the script...